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general description the ds1089l is a clock generator that produces a spread spectrum (dithered) square-wave output of fre- quencies from 130khz to 66.6mhz. the ds1089l is shipped from the factory programmed at a specific fre- quency. the ds1089l is pin-for-pin compatible with the ds1087l, however, the ds1089l dithers at equal per- centages above and below the center frequency. the user still has access to the internal frequency divider, selectable 1%, 2%, 4%, or 8% dithered output, dithering rate, and programmable output power- down/disable mode through an i 2 c*-compatible pro- gramming interface. all the device settings are stored in nonvolatile (nv) eeprom allowing it to operate in stand-alone applications. the ds1089l also has power-down and output-enable control pins for power- sensitive applications. applications automotive infotainment printers copiers computer peripherals pos terminals cable modems features factory-programmed square-wave generator from 33.3mhz to 66.6mhz center frequency remains constant independent of dither percentage no external timing components required emi reduction variable dither frequency user programmable down to 130khz with divider (dependent on master oscillator frequency) 1%, 2%, 4%, or 8% selectable dithered output glitchless output-enable control i 2 c-compatible serial interface nonvolatile settings power-down mode programmable output power-down/disable mode ds1089l 3.3v center spread-spectrum econoscillator ______________________________________________ maxim integrated products 1 rev 2; 5/06 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. * see standard frequency options table. ordering information pin configuration and typical operating circuits appear at end of data sheet. part temp range pin-package ds1089lu-yxx* -40 c to +85 c 8 ?op (118 mil) add ?t?for tape and reel. custom frequencies available, contact factory. standard frequency options part frequency (mhz) spread ( %) dither frequency ds1089lu-21g 14.7456 1 f mosc / 4096 ds1089lu-4cl 18.432 2 f mosc / 4096 ds1089lu-22f 24.576 1 f mosc / 2048 ds1089lu-23c 33.3 1 f mosc / 4096 ds1089lu-450 50.0 2 f mosc / 4096 ds1089lu-866 66.6 4 f mosc / 4096 ds1089lu-yxx fixed up to 66.6 1, 2, 4, or 8 f mosc / 2048 or 4096 or 8192 econoscillator is a trademark of dallas semiconductor corp. * i 2 c is a trademark of philips corp. purchase of i 2 c components from maxim integrated products, inc., or one of its sublicensed associated companies, conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips.
ds1089l 3.3v center spread-spectrum econoscillator 2 _____________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage on v cc relative to ground.......................-0.5v to +6.0v voltage on sprd, pdn , oe, sda, scl relative to ground* ........................-0.5v to (v cc + 0.5v) operating temperature range ...........................-40? to +85? programming temperature range .........................0? to +70? storage temperature range .............................-55? to +125? soldering temperature...................see ipc/jedec j-std-020a parameter symbol condition min typ max units supply voltage v cc (note 1) 2.7 3.3 3.6 v high-level input voltage (sda, scl, sprd, pdn , oe) v ih 0.7 x v cc v cc + 0.3 v low-level input voltage (sda, scl, sprd, pdn , oe) v il -0.3 0.3 x v cc v * this voltage must not exceed 6.0v. recommended operating conditions (t a = -40 c to +85 c) parameter symbol condition min typ max units high-level output voltage (out) v oh i oh = -4ma, v cc = min 2.4 v low-level output voltage (out) v ol i ol = 4ma 0.4 v v ol1 3ma sink current 0.4 low-level output voltage (sda) v ol2 6ma sink current 0.6 v high-level input current i ih v ih = v cc 1a low-level input current i il v il = 0v -1 a supply current (active) i cc c l = 15pf, f out = f moscmax 12 ma standby current (power-down) i ccq power-down mode 10 a dc electrical characteristics (v cc = +2.7v to +3.6v, t a = -40 c to +85 c)
ds1089l 3.3v center spread-spectrum econoscillator _____________________________________________________________________ 3 parameter symbol condition min typ max units internal master oscillator frequency f mosc 33.3 66.6 mhz master oscillator frequency tolerance v cc = 3.3v, t a = +25 c (notes 2, 10) -0. 5 +0. 5 % voltage frequency variation t a = +25 c (note 3) -0.75 +0.75 % t a = 0 c to +85 c -0.75 +0.75 temperature frequency variation (note 4) v cc = 3.3v, f out = f moscmax t a = -40 c to 0 c -2.00 +0.75 % j3 = j2 = gnd 1 j3 = gnd, j2 = v cc 2 j3 = v cc , j2 = gnd 4 dither frequency range (note 5) j3 = j2 = v cc 8 % j1 = gnd, j0 = v cc f mosc / 2048 j1 = v cc , j0 = gnd f mosc / 4096 dither frequency (note 5) f mod j1 = j0 = v cc f mosc / 8192 hz master oscillator characteristics (v cc = +2.7v to +3.6v, t a = -40 c to +85 c) parameter symbol condition min typ max units frequency stable after prescaler change 1 period power-up time t por + t stab (note 6) 40 200 s enable of out after exiting power-down mode t stab (note 6) 512 clock cycles out disabled after entering power-down mode t pdn 7s load capacitance c l 15 50 pf output duty cycle (f out ) 50 % ac electrical characteristics (v cc = +2.7v to +3.6v, t a = -40 c to +85 c) ? f f mosc mosc ? f f mosc ? f f mosc
ds1089l 3.3v center spread-spectrum econoscillatora 4 _____________________________________________________________________ note 1: all voltages are referenced to ground. note 2: this is the absolute accuracy of the master oscillator frequency at the default settings with spread disabled. note 3: this is the change that is observed in master oscillator frequency with changes in voltage at t a = +25 ? c. note 4: this is the change that is observed in master oscillator frequency with changes in temperature at v cc = 3.3v. note 5: the dither deviation of the master oscillator frequency is biderectional and results in an output frequency centered at the undithered frequency. note 6: this indicates the time elapsed between power-up and the output becoming active. an on-chip delay is intentionally intro- duced to allow the oscillator to stabilize. t stab is equivalent to 512 master clock cycles and will depend on the programmed master oscillator frequency. note 7: timing shown is for fast-mode (400khz) operation. this device is also backward compatible with i 2 c standard-mode timing. note 8: c b ? total capacitance of one bus line in picofarads. note 9: eeprom write time applies to all the eeprom memory and sram shadowed eeprom memory when wc = 0. the eeprom write time begins after a stop condition occurs. note 10: typical frequency shift due to aging is 0.25%. aging stressing includes level 1 moisture reflow conditioning (24hr) +125 ? c bake, 168hr +85 ? c/85 ? rh moisture soak, and three solder reflow passes +260 +0/-5?c peak) followed by 408hr max v cc biased 125 ? c htol, 500 temperature cycles at -55 ? c to +125 ? c, 96hr +130 ? c/85%rh/3,6v hast and 168hr +121 ? c/2 atm steam/unbiased autoclave. parameter symbol conditions min typ max units scl clock frequency f scl (note 7) 0 400 khz bus free time between stop and start conditions t buf 1.3 s hold time (repeated) start condition t hd:sta 0.6 s low period of scl t low 1.3 s high period of scl t high 0.6 s data hold time t hd:dat 0 0.9 s data setup time t su:dat 100 ns start setup time t su:sta 0.6 s sda and scl rise time t r (note 8) 20 + 0.1c b 300 ns sda and scl fall time t f (note 8) 20 + 0.1c b 300 ns stop setup time t su:sto 0.6 s sda and scl capacitive loading c b (note 8) 400 pf eeprom write time t wr (note 9) 10 20 ms ac electrical characteristics?i 2 c interface (v cc = +2.7v to +3.6v, t a = -40 ? c to +85 ? c, unless otherwise noted. timing referenced to v il(max) and v ih(min) .) parameter symbol condition min typ max units writes +70 ? c 10,000 nonvolatile memory characteristics (v cc = +2.7v to +3.6v)
ds1089l 3.3v center spread-spectrum econoscillator _____________________________________________________________________ 5 0 2 6 4 8 10 active supply current vs. supply voltage ds 1089l toc01 supply voltage (v) supply current (ma) 2.7 3.0 3.3 3.6 66mhz 50mhz 130khz 33mhz t a = +25 c, output unloaded 0 3 2 1 4 5 6 7 8 9 10 -40 10 -15 35 60 85 active supply current vs. temperature ds 1089l toc02 temperature ( c) supply current (ma) 66mhz 50mhz 130khz 33mhz t a = +25 c, output unloaded 0 1 1000 100 10 supply current vs. prescaler 10 4 2 8 6 ds 1089l toc03 prescale divider (decimal) supply current (ma) 3.6v 3.3v 2.7v t a = +25 c, f mosc = 50mhz, output unloaded 0 1 3 2 4 5 -40 10 -15 35 60 85 shutdown supply current vs. temperature ds 1089l toc04 temperature ( c) supply current ( a) v cc = 3.3v, pdn = gnd -0.50 -0.25 0 0.25 0.50 2.7 3.0 3.3 3.6 frequency % change vs. supply voltage ds 1089l toc05 supply voltage (v) frequency change (%) 66mhz 50mhz 130khz 33mhz t a = +25 c -0.8 -0.6 -0.2 -0.4 0 0.2 -40 10 -15 35 60 85 frequency % change vs. temperature ds 1089l toc06 temperature ( c) frequency change (%) 66mhz 50mhz 130khz 33mhz v cc = 3.3v typical operating characteristics (v cc = 3.3v, t a = +25 c, unless otherwise noted.)
pin description pin name function 1 out oscillator output 2 sprd dither enable. when the pin is high, the dither is enabled. when the pin is low, the dither is disabled. 3v cc power supply 4 gnd ground 5oe output enable. when the pin is high, the output buffer is enabled. when the pin is low, the output is disabled but the internal master oscillator is still on. 6 pdn ds1089l 3.3v center spread-spectrum econoscillator 6 _____________________________________________________________________ 48 50 54 52 56 58 -40 10 -15 35 60 85 duty cycle vs. temperature ds 1089l toc08 temperature ( c) duty cycle (%) 66mhz 50mhz 130khz 33mhz v cc = 3.3v 48 50 54 52 56 58 duty cycle vs. supply voltage ds 1089l toc07 supply voltage (v) duty cycle (%) 2.7 3.0 3.3 3.6 66mhz 50mhz 130khz 33mhz t a = +25 c -90 -70 -80 -40 -50 -60 -10 -20 -30 0 44 48 46 50 52 54 56 spectrum comparison (120khz bw, sample detect) ds 1089l toc09 frequency (mhz) power spectrum (dbm) no spread 1% 2% 4% 8% f mosc = 50mhz, dither rate = f mosc / 4096 typical operating characteristics (continued) (v cc = 3.3v, t a = +25 c, unless otherwise noted.)
ds1089l 3.3v center spread-spectrum econoscillator _____________________________________________________________________ 7 block diagram factory- programmed master oscillator 33.3mhz to 66.6mhz prescaler divide by 1, 2, 4, 8, 16, 32, 64, 128, or 256 triangle- wave generator i 2 c serial interface prescaler addr p0 p1 p2 p3 x lo/ hiz j0 j1 a0 a1 a2 wc x oe j2 j3 v cc v cc scl sda dither rate dither % eeprom write ee command out i 2 c address bits prescaler setting eeprom write control control registers f mod f osc f mosc f mosc f out synced output buffer output configuration output control oe pdn gnd sprd s/w gated output h/w gated output ds1089l detailed description master oscillator the internal master oscillator is capable of generating a square wave with a 33.3mhz to 66.6mhz frequency range. the master oscillator frequency (f mosc ) is factory programmed, and is specified in the ordering information . prescaler the user can program the prescaler divider to produce an output frequency (f out ) as low as 130khz using bits p0, p1, p2, and p3 in the prescaler register. the output frequency can be calculated using equation 1. any value programmed greater than 2 8 will be decod- ed as 2 8 . see table 1 for prescaler divider settings. equation 1 where x = p3, p2, p1, p0 output frequency hz f f osc mosc x () = 2 bits p3, p2, p1, p0 2 x =f out = f osc 0000 1 f mosc 0001 2 f mosc / 2 0010 4 f mosc / 4 0011 8 f mosc / 8 0100 16 f mosc / 16 0101 32 f mosc / 32 0110 64 f mosc / 64 0111 128 f mosc / 128 1000 256 f mosc / 256 1111 256 f mosc / 256 table 1. prescaler divider settings
ds1089l 3.3v center spread-spectrum econoscillator 8 _____________________________________________________________________ output control two user control signals control the output. the output enable pin (oe) gates the output buffer and the power- down pin ( pdn ) disables the master oscillator and turns off the output for power-sensitive applications. ( note: the power-down command must persist for at least two output frequency cycles plus 10s for deglitching purposes.) on power-up, the output is dis- abled until power is stable and the master oscillator has generated 512 clock cycles. additionally, the oe input is or ed with the oe bit in the addr register, allowing for either hardware or software gating of the output waveform (see the block diagram ). both controls feature a synchronous enable, which ensures that there are no output glitches when the out- put is enabled. the synchronous enable also ensures a constant time interval (for a given frequency setting) from an enable signal to the first output transition. dither generator the ds1089l has the ability to reduce radiated emis- sion peaks. the output frequency can be dithered by 1%, 2%, 4%, or 8% symmetrically around the pro- grammed center frequency. although the output fre- quency changes when the dither is enabled, the duty cycle does not change. the dither rate (f mod ) is controlled by the j0 and j1 bits in the prescaler register and is enabled with the sprd pin. the maximum spectral attenuation occurs when the prescaler is set to 1. the spectral attenuation is reduced by 2.7db for every factor of 2 that is used in the prescaler. this happens because the prescaler s divider function tends to average the dither in creating the lower frequency. however, the most stringent spec- tral emission limits are imposed on the higher frequen- cies where the prescaler is set to a low divider ratio. a triangle-wave generator injects an offset element into the master oscillator to dither its output. the dither rate can be calculated based on the master oscillator fre- quency (see equation 2). equation 2 where f mod = dither frequency, f mosc = master oscilla- tor frequency, and n = divider setting (see table 2). dither percentage settings the dither amplitude (measured in percentage of the master oscillator center frequency) is set using the j2 and j3 bits in the addr register. this circuit uses a sense current from the master oscillator bias circuit to adjust the amplitude of the triangle-wave signal to a voltage level that modulates the master oscillator to a percentage of its factory-programmed center frequen- cy. this percentage is set in the application to be 1%, 2%, 4%, or 8% (see table 3). the location of bits p3, p2, p1, p0, j1, and j0 in the prescaler register and bits j3 and j2 in the addr register are shown in the register summary section. f f mod mosc = n table 2. dither frequency settings bits j1, j0 dither frequency 00 no dither 01 f mosc / 2048 10 f mosc / 4096 11 f mosc / 8192 table 3. dither percentage settings bits j3, j2 dither amount 00 1% 01 2% 10 4% 11 8%
when dither is enabled (by selecting a dither frequency setting greater than 0 with sprd high), the master oscillator frequency is dithered around the center fre- quency by the selected percentage from the pro- grammed f mosc (see figure 2). for example, if f mosc is programmed to 40mhz (factory setting) and the dither amount is programmed to 1%, the frequency of f mosc will dither between 39.6mhz and 40.4mhz at a modulation frequency determined by the selected dither frequency. continuing with the same example, if j1 = 0 and j0 = 1, selecting f mosc / 2048, then the dither frequency would be 19.531khz. register summary the ds1089l registers are used to change the dither amount, output frequency, and slave address. a bit summary of the registers is shown in table 4. once pro- grammed into eeprom, the settings only need to be reprogrammed if it is desired to reconfigure the device. prescaler register bits 7 to 6: dither frequency. the j1 and j0 bits control the dither frequency applied to the output. see table 2 for divider settings. if either of bits j1 or j0 is high and sprd is high, dither is enabled. bit 5: output low or hi-z. the lo/ hiz bit determines the state of the output during power-down. while the output is deacti- vated, if the lo/ hiz bit is set to 0, the out- put will be high impedance (high-z). if the lo/ hiz bit is set to 1, the output will be driven low. bit 4: reserved. bits 3 to 0: prescaler divider. the prescaler bits (bits p3 to p0) divide the master oscillator fre- quency by 2 x where x can be from 0 to 8. any prescaler bit value entered that is greater than 8 will decode as 8. see table 1 for prescaler settings. addr register bits 7 to 6: dither percentage. the j3 and j2 bits control the selected dither amplitude (%). when both j3 and j2 are set to 0, the default dither rate is 1%. bit 5: output enable. the oe bit and the oe pin state determine if the output is on when the device is active ( pdn = v ih ). if ( oe = 0 or oe is high) and the pdn pin is high, the output will be driven. bit 4: reserved. bit 3: write control. the wc bit determines if the eeprom is to be written after register contents have been changed. if wc = 0 (default), eeprom is written automatically after a write. if wc = 1, the eeprom is only written when the write ee command is issued. see the write ee command section for more information. bits 2 to 0: address. the a0, a1, a2 bits determine the lower nibble of the i 2 c slave address. ds1089l 3.3v center spread-spectrum econoscillator _____________________________________________________________________ 9 if dither amount = 0% (+1, 2, 4, or 8% of f mosc ) programmed f mosc (-1, 2, 4, or 8% of f mosc ) dither amount (2, 4, 8, or 16%) time 1 f mod f mosc figure 2. output frequency vs. dither rate table 4. register summary register addr bit7 binary bit0 default access prescaler 02h j1 j0 lo/ hiz x p3 p2 p1 p0 xx00xxxxb r/w addr 0dh j3 j2 oe x wc a2 a1 a0 xx100000b r/w write ee 3fh no data x = ?on? care x = values depend on custom settings
ds1089l write ee command the write ee command is useful in closed-loop appli- cations where the registers are frequently written. in applications where the register contents are frequently written, the wc bit should be set to 1 to prevent wear- ing out the eeprom. regardless of the value of the wc bit, the value of the addr register is always written immediately to eeprom. when the write ee com- mand has been received, the contents of the registers are written into the eeprom, thus locking in the regis- ter settings. 3.3v center spread-spectrum econoscillator 10 ____________________________________________________________________ stop condition or repeated start condition repeated if more bytes are transferred ack start condition ack acknowledgement signal from receiver acknowledgement signal from receiver slave address msb scl sda r/w direction bit 12 678 9 12 89 3? figure 3. i 2 c data transfer protocol 1 0 1 1 r/w a0 a1 a2 msb lsb device identifier device address read/write bit figure 4. slave address byte i 2 c serial port operation
ds1089l 3.3v center spread-spectrum econoscillator ____________________________________________________________________ 11 sda scl t hd:sta t low t high t r t f t buf t hd:dat t su:dat repeated start t su:sta t hd:sta t su:sto t sp stop start figure 5. i 2 c ac characteristics slave ack 10 1 1 r/w a0* a1* slave ack a2* msb lsb device identifier device address read/ write msb lsb command/register address slave ack msb lsb b7 b6 b5 b4 b3 b2 b1 b0 slave ack stop *the address determined by a0, a1, and a2 must match the address set in the addr register. data typical i 2 c write transaction example i 2 c transactions (when a0, a1, and a2 are zero) a) single byte write -write prescaler register to 128 b) single byte read -read prescaler register start start start b0h b0h slave ack slave ack 02h 02h slave ack slave ack data slave ack stop 10110000 10110000 b7 b6 b5 b4 b3 b2 b1 b0 00000010 10000000 10000000 00000010 repeated start data master nack stop slave ack 10110001 b1h figure 6. i 2 c transactions applications information power-supply decoupling to achieve the best results when using the ds1089l, decouple the power supply with 0.01f and 0.1f high-quality, ceramic, surface-mount capacitors. surface-mount components minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high-frequency response for decoupling applications. these capacitors should be placed as close to the v cc and gnd pins as possible. stand-alone mode scl and sda cannot be left floating even in stand- alone mode. if the ds1089l will never need to be pro- grammed in-circuit, including during production testing, sda and scl can be connected high.
ds1089l 3.3v center spread-spectrum econoscillator maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. is a registered trademark of dallas semiconductor corporation. package information for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo . chip topology transistor count: 5985 substrate connected to ground pdn oe gnd 1 2 8 7 scl sda sprd v cc out top view 3 4 6 5 ds1089l pin configuration out sprd gnd oe pdn sda scl v cc v cc v cc v cc 4.7k ? 4.7k ? 2-wire interface dithered 130khz to 66.6mhz output decoupling capacitors (0.1 f and 0.01 f) *sda and scl can be connected directly high if the ds1089l never needs to be programmed in-circuit, including during production testing. ds1089l out n.c. sprd gnd oe pdn sda* scl* v cc v cc v cc dithered 130khz to 66.6mhz output xtl2/osc2 xtl1/osc1 microprocessor decoupling capacitors (0.1 f and 0.01 f) ds1089l typical operating circuits processor-controlled mode stand-alone mode

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